The subject matter of this application is directed to switching schemes for unit elements in digital to analog converters (DACs), and more particularly to switching schemes for tri-level unit elements that mitigates intersymbol interference (ISI).
Digital to analog converters (DACs) receive a digital input signal and provide an analog output signal (e.g., current, voltage or electric charge) representing the digital signal. For simplicity and flexibility, current steering architectures may be used in DACs. In one design, the DAC includes multiple two-level current steering unit elements (e.g., 1-bit DAC). One unit element can be provided for each quantization level of the digital input signal. Depending on the value of the digital input signal, switches are operated to control the contribution of each unit element to provide a positive current or a negative current to the output signal. The outputs of the unit elements are combined to provide an analog output signal representing the digital input signal.
In another design, tri-level current steering unit elements are used to provide the analog output signal. Each tri-level unit element can include a pair of current sources (positive and negative) for each quantization level of the digital input signal. Depending on the value of the digital input signal, each tri-element unit element provides either a positive current, a negative current or no current to the output signal. Tri-level unit elements in DACs provide noise and power advantages over the more conventional two-level unit elements, where all the unit elements are always connected to the output.
One of the sources of error in DACs is intersymbol interference (ISI). ISI is a form of distortion in which symbols of the digital signal interfere with subsequent symbols. ISI may be present when noise on the outputs depends on switching activity of the circuit elements, which depend on information content of the signals passing through the circuit. In a DAC, ISI occurs when the output for a particular clock period is a function not only of the digital input signal applied to the DAC for that clock period, but also a function of the digital input signal applied for the preceding clock periods. In particular, the ISI is the result of unequal rise and fall times in the waveforms of the current delivered to the output by each unit element.
FIG. 1 illustrates a circuit for a switching scheme to control current sources in a tri-level unit element. The tri-level unit element 100 may include outputs 110, 120, current sources 130, 140, a current dump node 150 and six switches A, B, C, D, E and F. The switches A, B, C, D, E and F may be controlled to provide three states of operation for the unit element 100 by coupling the current sources 130, 140 to one of the outputs 110, 120 and the current dump node 150. The switches may be controlled based on the digital input signal (not shown in FIG. 1). In a first state, the unit element 100 may provide current to the output 110 and drain current from the output 120. In the second state, the unit element 100 may provide current to the output 120 and drain current from the output 110. In the third state, the unit element 100 may be inert by neither supplying current to nor draining current from either output terminal 110, 120 (i.e., coupling the current sources 130, 140 to the current dump node 150).
In FIG. 1, ISI may be caused by the drain capacitance of the current sources 130, 140 and/or the capacitance at the sources of the switches A, B, C, D, E and F, and the associated feed through to this capacitance due to the switching of the current sources 130, 140. ISI may also be caused when the current sources 130, 140 that have not been used for some time, are subsequently chosen to be used. Thus, the output at a particular clock period becomes a function not only of the digital input signal for the current clock period, but also a function of the digital input signal applied for one or more preceding clock periods.
Several techniques have been proposed to mitigate ISI. For example, delayed driving schemes of the switches controlling the current sources have been used to maintain a crossing point of the switches' gate drive relative to the switching threshold. However, the delayed driving schemes do not track well with process, voltage and/or temperature variations. Another proposed solution is a return to zero technique, where the output of each unit element is forced to start from zero, reach its final value, and return to zero within a single clock period. However, this technique introduces large steps into the output which may increase the slew rate and bandwidth requirements for a subsequent circuit stage (e.g., an amplifier). Duel return to zero techniques were proposed to overcome the disadvantages of the return to zero technique, where for each bit clock period, two or more return to zero signals are generated for each input bit. However, this technique significantly increases the silicon area and consumes more power. To overcome the disadvantages of the duel return to zero technique, a return to hold technique was proposed. The return to hold technique includes two phases. The first phase is a hold phase involving a disconnecting and updating the current sources to allow them to settle. The second phase involves connecting the current sources to the outputs after the current sources are settled. However, with increased operating frequencies, the return to hold technique has trouble settling with a smaller hold phase.
Accordingly, there is a need in the art for a switching scheme to control tri-level unit element and mitigate ISI while allowing for higher frequency operation.